1. Field of the Invention
This invention relates to interposer substrates, and, more particularly, to an interposer substrate for a package on package (PoP) and a method for fabricating the same.
2. Description of Related Art
With the evolution of technology in the semiconductor package, a semiconductor device has been developed different types of packages. In order to enhance electrical function and to save packaging space, a plurality of package structures are stacked so as to form a package on package (PoP). This packaging method can accomplish the heterogeneous integration features of a system in package (SiP), such that electronic components with different functions, such as memory, central processors, graphics processors, video processors and the like, are suitable for thin electronic products by stacking design so as to achieve the integration of the system.
In the early period, a package on package is formed from a memory packaging member (memory IC) by stacking a plurality of solder balls on a logic packaging member (logic IC). With the requirements of more compact and improve function of electronic products, the layout of the memory packaging member is more dense with nano units, such that the distance between contacts is smaller. However, the distance of the logic packaging member with micrometer units cannot be decreased to correspond to the distance of the memory packaging member, such that the memory packaging member with high circuit density has no suitable logic packaging member, and that electronic products cannot be effectively produced.
Therefore, in order to overcome the above problem, an interposer substrate 10 is disposed between the memory packaging member 11 and the logic packaging member 12. As illustrated in FIG. 1, the bottom end of the interposer substrate 10 is electrically connected with the logic packaging member 12 having a logic chip 120 with larger distance, and the upper end of the interposer substrate 10 is electrically connected with the memory packaging member 11 having a memory chip 110 with smaller distance.
However, in the prior package on package 1, a plurality of solder balls 13 are used as supporting and electrically connecting members. Further, as the number of contact of electronic products (i.e., I/O) are increasing, and the size of packaging member is constant, the distance between the solder balls 13 has to be decreased, such that bridging phenomenon is easily occurred during reflowing and thus short circuit is induced, and that it further results in extremely low product yield and poor reliability.
Therefore, it is developed that the solder ball 13 is replaced by a copper pillar. The height of the copper pillars can remain consistency through the characteristic of the copper pillar not deforming during reflowing, such that the bridging problem can be avoided, and the product yield can be increased.
FIGS. 1A-1D are schematic sectional views of a method of fabricating an interposer substrate 10 according to the prior art.
As illustrated in FIG. 1A, a plate 10′ such as a copper foil substrate is penetrated so as to form a plurality of vias 100.
As illustrated in FIG. 1B, wiring layers 15 are formed on two sides of the plate 10′ through the copper foil 10a, and a plurality of conducting holes 16 are formed in the vias 100 so as to be electrically connected to the wiring layers 15.
As illustrated in FIG. 1C, an insulating protection layer 17 is formed on the plate 10′ and the wiring layer 15 and exposes a portion of the wiring layer 15 for an electrical contact pad 150 to be provided thereon.
As illustrated in FIG. 1D, a copper pillar 14 is formed on the electrical contact pad 150 in an electroplating process.
However, the method of fabricating the interposer substrate 10 according to the prior art is complicated, such as forming the vias 100, such that the cost is high. Besides, an additional conducting layer 140 has to be formed so as to make copper pillars 14 in an electroplating process on one side or two side under requirements. Therefore, a little bit of conducting layer 140 may usually be remained when unnecessary conducting layer 140 is removed, such that the conductivity of the copper pillars 14 may be affected. For example, the rest of the conducting layer 140 may electrically connect adjacent copper pillars 14, and thus resulting in short circuit. In the consequence, the overall conductivity of the interposer substrate 10 may decrease.
Further, the thickness of the interposer substrate 10 may be limited under the consideration of the plate 10′ (i.e., the core layer). For example, the interposer substrate is hard to be made thin. Accordingly, the interposer substrate not only is hard to be produced but also easily has problems of damages to the plate 10′ when the thickness of the interposer substrate is thinner (below 130 um).
Further, the line width/line space (L/S) design of the wiring layer 15 is easily limited. In general, the smallest line width/line space of the fabricating process of a substrate is merely 12/12 um. However, when the L/S is below 25/25 um, the product yield is readily affected.
Therefore, how to overcome the various problems of the prior art has become the emergency issues that need to be resolved.